A quad-data-rate static random access memory (QDR™ SRAM) device has separate data input and data output buses that operate simultaneously. Each data bus can operate on two words of data per clock cycle, doubling its data rate. Because both buses operate in parallel, the device can operate on four bus widths of data per clock cycle. The QDR SRAM device can operate in burst-of-two or burst-of-four modes. In the burst-of-two mode, each read/write command causes data having twice the bus width to be read from or written to the memory device. In the burst-of-four mode, each read/write command causes data having four times the bus width to be read from or written to the memory device.
A low latency dynamic random access memory (DRAM) device has circuitry to reduce latency, i.e., reduce the time between the beginning of the access cycle and the availability of data. Low latency DRAM devices include reduced latency DRAM (RLDRAM™) devices and fast cycle RAM (FCRAM™) devices, both operating with double data rate interfaces. These memory devices can have multiple internal memory banks that provide higher bandwidths while still allowing random access within each bank.
QRD SRAM and low latency DRAM devices are often used in network applications. For example, they can be used for storing lookup tables and network control information. The QDR SRAM, RLDRAM, and FCRAM devices have different structures, different pin assignments, and require different timing requirements for read/write access of data.